1. Field of the Invention
The present invention relates to the storage of information by altering the operational characteristics of a transistor within an array of memory transistors and, more particularly, to a read only memory (ROM).
2. Description of the Related Art
Difficulties are encountered when attempting to increase the storage density of mask ROMs following conventional strategies. Alignment during mask ROM programming is important to the proper storage of information within mask ROMS. Difficulties encountered in achieving precise alignment in a production environment makes it difficult to further reduce the size of the field effect transistors used in forming the mask ROM while still obtaining acceptable yields. Certain of the difficulties in reducing the size of mask ROMs are discussed as follows.
A portion of a mask ROM 10 is schematically illustrated in FIG. 1 as including a parallel array of word lines WL and a parallel array of bit lines BL. Programming of the ROM 10 is performed by selecting the performance characteristics of the circuit elements located at the intersections between the word lines WL and the bit lines BL. In the illustrated ROM, field effect transistors (FETs) having a drain connected to a bit line BL and a gate connected to a word line WL are located at each of the intersections between the word lines and the bit lines. Information is stored by selecting the threshold voltages of the field effect transistors formed at each of the intersections. A logical zero may be stored at the intersection of WL0 and BL0 by causing the field effect transistor 12 to have a relatively low threshold voltage; a logical one may be stored at the intersection 14 of word line WL0 and bit line BL1 by causing the FET at that location to have a relatively high threshold voltage.
Data read operations consist of applying a potential to both the word line and the bit line associated with a particular intersection or memory location, and may measure the potential on the bit line to determine if the transistor has a low threshold voltage. For example, if a low threshold voltage FET is present at the selected memory location, the potential applied to the gate of the selected FET drains the charge from the bit line, reducing the potential on the bit line to a level that is read as a logical zero. In this example, if a high threshold voltage FET is present at the selected intersection, the potential applied to the gate will not render the FET conductive so that the potential on the corresponding bit line will remain high and the data bit read out will be a logical one. ROMs may alternately perform the data read operation as a comparison between the bit line voltage and a reference voltage or the ROMs may perform the data read operation as a comparison of the threshold characteristics of the memory transistor against one or more reference transistors having selected threshold voltage characteristics.
FIG. 2 illustrates a conventional configuration of a portion of the FIG. 1 ROM. The bit lines may be a parallel array of xe2x80x9cburiedxe2x80x9d lines 22, 24, 26 and 28 formed as N+ implantations into a P-type silicon substrate 20. Lines 22 and 26 are connected to a potential source V and lines 24 and 28 are connected to a lower potential source, such as ground, so that lines 22 and 26 are FET drains and lines 24 and 28 are the sources of the FETs formed to store data in the illustrated ROM. A second array of conductive lines WL0, WL1, etc., is formed from, for example, a layer of doped polysilicon deposited on an insulation layer formed over the buried NE lines 22, 24, 26 and 28. The conductive lines WL0, WL1, etc., are formed perpendicular to the implanted buried N+ bit lines and will form the gates of the FETs of the ROM. To form lower threshold voltage transistors at selected ones 30 of the potential transistor positions and to form relatively high threshold voltage transistors at the other potential transistor positions 32, processing differences must be introduced between the regions 30 and 32.
FIG. 3 illustrates one conventional method of causing lower threshold voltage transistors to be formed at certain locations 30 (logical zeros) while forming relative high threshold voltage transistors at other locations 32 (logical ones). In FIG. 3, buried bit lines 22, 24, 26 and 28 form the sources and drains of the memory FETs, oxide layer 40 forms the gate insulator for the FETs, and word line WL1 is the gate for the FETs. For those positions 30 at which a lower threshold voltage transistor is to be formed, the insulation layer 42 formed between the adjacent bit line implantations is made thin. Thus, insulation layer 42 is silicon oxide formed to a conventional gate oxide thickness. For those positions 32 at which a relatively high threshold voltage transistor is to be formed, the insulation layer 44 between adjacent bit line implantations is made sufficiently thick that the FET consisting of source and drain regions 24 and 26, insulator 44 and gate WL1 has a measurably higher threshold voltage. Accordingly, programming for the FIG. 3 type of FET is accomplished by forming thick insulating films over the channel regions where high threshold voltage FETs are to be formed and growing thin insulator films over those FET channel regions where lower threshold voltage FETs are to be formed. Programming the FIG. 3 mask ROM typically requires the formation of a mask which exposes those potential channel regions at which thick oxides are to be formed, growth of a thick oxide, removal of the mask, and growth of thinner gate oxides over those locations at which FETs are to be formed. This programming technique relies on the precise alignment of the mask with respect to the implantations to ensure that the thin oxide layer completely covers the channel regions at the appropriate positions. Misalignment in any direction can alter the characterization of desired FETs or form FETs where none were to be formed. In addition, it is difficult to form sufficiently thick insulating films for small cell sizes, so that it is difficult to increase the cell density using this programming technique. As such, it is increasingly difficult to implement this programming technique for smaller design rules.
FIG. 4 illustrates a second method for selecting the threshold voltage characteristics of the transistors to program the ROM illustrated in FIGS. 1 and 2. The FIG. 4 ROM has a uniformly thin insulation layer over all of the channel regions of the FETs in the matrix. The threshold voltages of the FETs are selected by implanting different impurity levels into the channel regions of the transistors. For example, if the transistor would normally require a threshold adjust implant for acceptable operation, then programming of the ROM might consist of implanting an appropriate level of dopants into the channel regions of the FETs to be formed (logical zeros) and no implant is made into the channel regions of the FETs that are to have high threshold voltages (logical ones). If, on the other hand, no implant is necessary to enable the normal operation of a FET or if the difference between an unimplanted FET and a FET with a threshold adjust implant is too small to allow discrimination between implanted and unimplanted FETs, then an implant is made into the channels of those FETs that are not to be formed. Such an implant would be of a kind that increases the threshold voltage of the FET.
The processes for forming this ROM and for programming the ROM are now described. First, a mask is formed using photolithography on the substrate to expose the portions of the substrate into which dopants are implanted to define the buried N+ layers. After the mask is removed, a uniform gate oxide is grown on the surface of the substrate, and then a layer of polysilicon is deposited over the gate oxide layer and the entire gate polysilicon layer is doped N-type with, for example, a phosphorus implant or by diffusion from POCl3. Typically, a layer of a refractory metal or a refractory metal silicide such as tungsten silicide is then deposited over the doped polysilicon layer to further reduce the resistivity of the gate material. A gate mask is formed and the tungsten silicide and doped polysilicon layer are etched to define the word lines which also serve as the gates for the FETs of the ROM. After the word lines are formed, additional processing is performed to form support circuitry and then a mask is formed to define the regions into which the ROM programming implantation is to be made. Alternately, the ROM programming implantation could be made at different points in the processing of the ROM implantation.
When any type of selective channel implant is used to program the FIG. 4 ROM, it is necessary to form a mask over the ROM which exposes the channels of the FETs into which the implants are made. Several problems can occur in the conventional implantation programming technique which preclude this technology from being scaled down for use in smaller design rules. Implants into the channel regions must be annealed to activate the impurities, and the implants tend to diffuse during the anneal. Diffusion from the implant regions parallel to the bit lines limits how closely word lines can be spaced, which in turn limits the extent to which the ROM cell can be miniaturized.
Other difficulties with the implantation programming technique arise from possible misalignment of the programming mask. Mask misalignment along the bit line direction, such as that illustrated in FIG. 5, can lead to the introduction of impurities from an intended implantation region into an adjacent region. If the adjacent region represents a memory location for which implantation should be made, then this misalignment can generate an error, particularly when the misalignment is coupled with the subsequent diffusion of impurities. The need to provide an allowance for the type of misalignment illustrated in FIG. 5 and to provide an allowance for dopant diffusion limits how closely word lines can be spaced in the mask ROM.
A second type of mask error, arising either from misalignment or from a mask formation error, is illustrated in FIG. 6. Implantations into the channel region are not self-aligned to the buried N+ lines so that misalignment of the edge of the mask opening defining the implantation along the word line direction is a possible source of error. To limit the possibility of this error occurring, allowances must be made in the size of the implantation mask to increase the tolerance limits for mask placement. The provision of excess mask tolerances limits how closely bit lines can be spaced. Accordingly, it is desirable to develop a mask ROM less dependent on mask alignment and more compatible with increasing the storage density of a mask ROM.
One aspect of the present invention provides a memory device comprising a first transistor having a drain, a source and a gate and a second transistor having a drain, a source and a gate. The first and second transistors have a common drain, a common source, or both a common drain and a common source. The gate of the first transistor comprises polysilicon doped P-type and the gate of the second transistor comprises polysilicon doped N-type. In accordance with a further aspect of the present invention, the gates of the first and second transistor consist of a lower polysilicon layer and a second layer of a conductive material which makes ohmic contact to N-type polysilicon and P-type polysilicon.
Another embodiment of the present invention memory device comprises a first transistor and a second transistor. The gate of the first transistor comprises a lower polysilicon layer doped N-type and an upper layer of conductive material, the upper layer of conductive material forming an ohmic contact with the N-type polysilicon layer. The gate of the second transistor comprises a lower polysilicon layer doped P-type and the upper layer of conductive material, the upper layer of conductive material forming an ohmic contact with the P-type polysilicon layer. The first and second transistors have a common drain or a common source, a P/N junction is formed between the polysilicon layers of the gates of the first and second transistors, and the upper layer of the gate of the first transistor and the upper layer of the gate of the second transistor comprise a single wiring line.
The present invention also provides a memory device having a first column of first transistors, each first transistor having a first drain, a first source and a first gate, the first drains of the first transistors coupled together to form a first drain bit line and the first sources of the first transistors coupled together to form a first source bit line. A second column includes a plurality of second transistors, with each second transistor having a second drain, a second source and a second gate, the second drains of the second transistors coupled together to form a second drain bit line and the second sources of the second transistors coupled together to form a second source bit line. The first gate of each of the first transistors and the second gate of a corresponding one of the second transistors comprise a continuous polysilicon wiring line, and a plurality of P/N junctions are formed between the first gates and the corresponding second gates.
According to a different aspect of the present invention, a memory device includes a first column comprising a plurality of first transistors, each first transistor having a first drain, a first source and a first gate. A second column includes a plurality of second transistors, each second transistor having a second drain, a second source and a second gate. The first gate of each of the first transistors and the second gate of a corresponding one of the second transistors comprise a continuous wiring line, wherein at least one of the first gates has a first work function such that the first transistor has a first threshold voltage and wherein at least one of the second gates has a second work function such that the second transistor has a second threshold voltage, the first work function being sufficiently higher than the second work function so that the first threshold voltage is higher than the second threshold voltage by at least approximately one volt.
In accordance with another preferred embodiment, a mask ROM comprises a voltage source providing a reference voltage and first and second transistors. The first transistor has a first gate formed over a first channel region and comprising a first material having a first work function with respect to a substrate material so that the first transistor has a first threshold voltage. The second transistor has a second gate formed over a second channel region, the second gate comprising a second material having a second work function with respect to the substrate material so that the second transistor has a second transistor voltage. The first transistor is in an ON state when the reference voltage is applied to the first gate and the second transistor is in an OFF state when the reference voltage is applied to the second gate.
Another aspect of the present invention provides a method of storing information in a mask ROM. An encoding mask is formed on a layer of polysilicon formed on a gate oxide layer covering a substrate, and the encoding mask provides a plurality of openings corresponding to possible memory locations within the mask ROM. The polysilicon is doped through the openings provided in the encoding mask and then the mask is removed. The method forms a layer of conductive material over at least part of the layer of polysilicon and then etches the layer of conductive material and the layer of polysilicon to form gate electrodes. In a further aspect of the invention, the layer of polysilicon is blanket doped with a first dopant of a first conductivity type and doping the polysilicon through the openings provided in the encoding mask locally alters the polysilicon to a second conductivity type.